FIG. 1 shows a conventional semiconductor integrated circuit, particularly the details of a data read/write circuit portion for memory cells. As shown in FIG. 1, memory cells 1 are disposed in a matrix configuration. Any one of memory cells 1 can be selected by a row decoder 2 and a column decoder 3. A first sense amplifier 7 and a second sense amplifier/output buffer 8 are used when reading data from a memory cell 1. These circuits 7 and 8 read the data and send it to an input/output terminal 4. A data input circuit/first write buffer 5 and a second write buffer 6 are used when writing data to a memory cell 1. These circuits 5 and 6 write data from the input/output terminal 4 to a memory cell 1. Data read/write is selected by a read/write selector 9. First to fourth MOS transistors Tr1 to Tr4 turn on upon reception of an equalizing pulse outputted from an equalizing pulse generator 10 when an address for selecting a memory cell 1 changes. When the MOS transistors Tr1 to Tr4 are turned on, data accessed during a previous cycle is invalidated. The MOS transistors Tr1 and Tr2 equalize complementary data lines.
FIGS. 1A and 1B show the details of the circuits 9 and 10, respectively. Signals applied to the circuit 10 are generated in a circuit shown in FIG. 1C. In FIG. 1C, circuits labeled as the same reference numeral "15" show the same circuits.
With the circuit arrangement constructed as above, in reading data, the read/write selector 9 makes active the first sense amplifier 7 and second sense amplifier/output buffer 8, and makes inactive the data input circuit/first write buffer 5 and second write buffer 6. In this condition, the state (data) of a memory cell selected by the row decoder 2 and column decoder 3 is transferred to the first sense amplifier 7. This state is sent to the input/output terminal 4 via the second sense amplifier/output buffer 8. On the other hand, in writing data, the read/write selector 9 makes inactive the first sense amplifier 7 and second sense amplifier/output buffer 8, and makes active the data input circuit/first write buffer 5 and second write buffer 6. In this condition, data inputted from the input/output terminal 4 is written in a memory cell 1 selected by the row decoder 2 and column decoder 3. An equalizing pulse from the equalizing pulse generator 10 is supplied to the first to fourth MOS transistors Tr1 to Tr4 when an address is changed. Therefore, data in a memory cell 1 accessed at the preceding cycle is invalidated, to thus improve access speed.
The operation of the circuit shown in FIG. 1 is illustrated in a timing chart FIG. 1D in detail.
A serial connection of multiple stages including the first sense amplifier 7 and second sense amplifier/output buffer 8 is used in reading data. With this arrangement, the length of data line is divided and shortened, so that load capacitance to be driven by a memory cell 1 can be reduced and the data can be efficiently amplified. Similarly, a serial connection of multiple stages including the data input circuit/first write buffer 5 and second write buffer 6 is used in writing data. This arrangement results from substantially the same reason described above.
Conventionally, a multiple stage configuration has been applied to both reading and writing data via common data lines. A write buffer is therefore required to be provided for each data read stage. This results in an increased area of circuit pattern and an increased power consumption by a plurality stage of write buffers.